1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to the structure of a capacitor of a semiconductor device and a method for manufacturing the same. These are suited to enhance the characteristics and reliability of a semiconductor device by increasing the capacitance in a highly integrated device such as a dynamic random access memory device (DRAM).
2. Discussion of the Related Art
In general, a DRAM has a simple structure in which each cell includes one transistor and one capacitor. Such a structure is profitable in that it provides for large capacitance at a low cost.
Accordingly, DRAMs are widely used for various kinds of electronic products, including computers, and the application range thereof is continuously expanding.
At the present time, 16 Mb DRAMs and 64 Mb DRAMs are in mass production. 256 Mb DRAMs and 1 Gb DRAMs, on the other hand, are in an earlier stage of development.
As the integration of DRAMs increases, the capacitor area in the cell area rapidly decreases. Therefore, techniques of manufacturing a capacitor which obtain the same capacitance in a reduced area are emerging as one of the most important areas for enhancing the integration of DRAMs.
Hereinafter, a capacitor of a general DRAM will be described with reference to the attached drawings.
FIGS. 1a and 1b are cross-sectional views showing the structure of a general capacitor having a high dielectric film.
Generally, in manufacturing a capacitor, studies with respect to usage of materials having a high dielectric constant, such as BaSrTiO.sub.3 (BST), BaTiO.sub.3, SrTiO.sub.3, and PbZrO.sub.3, have been actively proceeding. However, in case of using these materials with a high dielectric constant as a dielectric film of a capacitor, the following restrictions apply.
First, if a polysilicon is used as a storage node electrode (lower electrode), an interface oxide film is formed between the electrode and the high dielectric film. This will have an adverse effect on the utility of the device. Further, since the depositing of the high dielectric film is performed at a high temperature of 600-700.degree. C., materials having a high melting point and a non-oxidizing characteristic have to be used to form the electrode.
Accordingly, manufacturing a capacitor by using a high dielectric material needs improvement both in the structure of the storage node electrode and in the development of the process therewith.
In other words, when using a polysilicon electrode, an electrode of a multi-layer structure in which a barrier layer is formed should be adopted to prevent the formation of the interface oxide film between the dielectric film and the electrode.
Further, in order to form the electrode by using materials such as Pt, Pd, Rh, and Ru, etc., the development of the etching process should be preceded. But at present, this method does not yield successful results.
FIG. 1a shows a typical capacitor having a high dielectric film. An example of this is disclosed in IEDM'91, "A Stacked Capacitor With (Ba.sub.x Sr.sub.1-x)TiO.sub.3 for 256 M DRAM," by Koyanma et al., pp. 823-826.
With reference to FIG. 1a, a field oxide film 2 is formed on a device-isolating region of a semiconductor substrate 1. Impurity diffusion regions 3a and 3b having an LDD (lightly doped drain) structure are formed in the semiconductor substrate 1 on both sides of a gate electrode 4 formed on an active region. Through a contact hole of an interlayer insulating film 6 formed on the entire surface of the semiconductor substrate, a plug 5 for connecting impurity diffusion regions 3a and 3b with an upper electrode is formed. A barrier metal layer 7a consisting of TiN is formed to a predetermined width on a portion of the interlayer insulating film 6 including the plug 5. A lower electrode 7b consisting of Pt is formed on the barrier metal layer 7a. A high dielectric film 8 consisting of BST is formed over the entire surface of the capacitor area. An upper electrode 9 consisting of Pt is formed on the high dielectric film 8, thereby finishing the capacitor.
In the aforementioned capacitor having the high dielectric film, poor step coverage at a bent part (A) of the high dielectric film 8 consisting of BST can cause a leakage current.
At a part (B) where the barrier metal layer 7a is exposed, when depositing the high dielectric film 8 consisting of BST, the barrier metal layer 7a consisting of TiN or Ta is oxidized to increase a contact resistance. Further, the adhesion of the barrier metal layer 7a and the lower electrode 7b is weakened, so that lower electrode 7b may be inclined to be lifted.
In order to counter the aforementioned disadvantages of the capacitor having the high dielectric film, a suggested structure is shown in FIG. 1b.
FIG. 1b shows the structure of a capacitor corresponding to that disclosed in U.S. Pat. No. 5,335,138. A field oxide film 2 is formed on a device-isolating region of a semiconductor substrate 1. Impurity diffusion regions 3a and 3b having an LDD (lightly doped drain) structure are formed in the semiconductor substrate 1 on both sides of a gate electrode 4 formed on an active region. Through a contact hole of an interlayer insulating film 6 formed on the entire surface of the semiconductor substrate, a plug 5 for connecting impurity diffusion regions 3a and 3b with an upper electrode is formed. A barrier metal layer 7a consisting of TiN is formed to a predetermined width on the interlayer insulating film 6 including the plug 5. A lower electrode 7b consisting of Pt is formed on the barrier metal layer 7a. A conductive sidewall 10 is formed on the side of the barrier metal layer 7a and the lower electrode 7b. A high dielectric film 8 consisting of BST is formed on the entire surface of a capacitor area. An upper electrode 9 consisting of Pt is formed on the high dielectric film 8, thereby finishing the capacitor.
In the above capacitor structure, the conductive sidewall 10 is formed on the side of the barrier metal layer 7a and the lower electrode 7b for solving the problems of the increase in the leakage current and the oxidization of the barrier metal layer. The conductive sidewall 10 may be formed of conductive materials such as silicon nitride.
In the capacitor having the high dielectric film as described above, the high dielectric film should be deposited to a proper thickness to solve the problem of the leakage current caused due to the poor step coverage of the conductive sidewall 10. As a result of this, however, the effective capacitance of the capacitor is decreased because the capacitance of the main surface decreases as the thickness of the dielectric film of the top surface of the electrode increases.
In addition to the aforementioned problem, the above conventional capacitor having the high dielectric film has a simple s tack-type structure. Thus, it is difficult to obtain the capacitance required for a unit cell in the capacitor forming region which is reduced according to the increase in the integration of memory devices.